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2007 Microchip Technology Inc.

DS39599G-page 133

PIC18F2220/2320/4220/4320

15.0 CAPTURE/COMPARE/PWM

(CCP) MODULES

The standard CCP (Capture/Compare/PWM) module

contains a 16-bit register that can operate as a 16-bit

Capture register, a 16-bit Compare register or a PWM

Master/Slave Duty Cycle register. Table 15-1 shows

the timer resources required for each of the CCP

module modes.

The operation of CCP1 is identical to that of CCP2, with

the exception of the Special Event Trigger. Therefore,

operation of a CCP module is described with respect to

CCP1 except where noted. Table 15-2 shows the

interaction of the CCP modules.

Note:

In 28-pin devices, both CCP1 and CCP2

function as standard CCP modules. In

40-pin devices, CCP1 is implemented as

an Enhanced CCP module, offering addi-

tional capabilities in PWM mode. Capture

and Compare modes are identical in all

modules regardless of the device.

Please see Section 16.0 “Enhanced

Capture/Compare/PWM (ECCP) Mod-

ule” for a discussion of the enhanced

PWM capabilities of the CCP1 module.

REGISTER 15-1:

CCPxCON: CCPx CONTROL REGISTER

U-0

R/W-0

—

DCxB1

DCxB0

CCPxM3

CCPxM2

CCPxM1

CCPxM0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

Unimplemented: Read as ‘0’

bit 5-4

DCxB1:DCxB0: PWM Duty Cycle Bit 1 and Bit 0 for CCPx Module

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs of the duty

cycle are found in CCPR1L.

bit 3-0

CCPxM3:CCPxM0: CCPx Mode Select bits

0000 = Capture/Compare/PWM disabled (resets CCPx module)

0001 = Reserved

0010 = Compare mode: toggle output on match (CCPxIF bit is set)

0011 = Reserved

0100 = Capture mode: every falling edge

0101 = Capture mode: every rising edge

0110 = Capture mode: every 4th rising edge

0111 = Capture mode: every 16th rising edge

1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit

is set)

1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit

is set)

1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin

operates as a port pin for input and output)

1011 = Compare mode: trigger special event (CCPxIF bit is set)

11xx =PWM mode

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